Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow

ABSTRACT

An apparatus and method to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners that have a base corner with two pairs of off-corners. The approach of the present invention does not add any extra work in cell library characterization, while in the mean it increases the accuracy of the delay calculation and the library generation at corners other than standard corners.

CROSS-REFERENCE TO RELATED APPLICATIONS

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BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates generally to the art of microelectronicintegrated circuits. In particular, the present invention relates to theart of computing delays for cells in ASICs.

2. Description of Related Art

An integrated circuit chip (hereafter referred to as an “integratedcircuit” (IC), “ASIC”, or a “chip”) comprises cells and connectionsbetween the cells formed on a surface of a semiconductor substrate. TheIC may include a large number of cells and require complex connectionsbetween the cells.

A cell is a group of one or more circuit elements such as transistors,capacitors, and other basic circuit elements grouped to perform afunction. Each of the cells of an IC may have one or more pins, each ofwhich, in turn, may be connected to one or more other pins of the IC bywires. The wires connecting the pins of the IC are also formed on thesurface of the chip.

A net is a set of two or more pins which must be connected. Because atypical chip has thousands, tens of thousands, or hundreds of thousandsof pins which must be connected in various combinations, the chip alsoincludes definitions of thousands, tens of thousands, or hundreds ofthousands of nets, or sets of pins. All the pins of a net must beconnected. The number of the nets for a chip is typically in the sameorder as the order of the number of cells on that chip. Commonly, amajority of the nets include only two pins to be connected; however,many nets comprise three or more pins. Some nets may include hundreds ofpins to be connected. A netlist is a list of nets for a chip; moregenerally a netlist is a description of the logic cells and theirconnections.

Microelectronic integrated circuits consist of a large number ofelectronic components that are fabricated by layering several differentmaterials on a silicon base or wafer. The design of an integratedcircuit transforms a circuit description into a geometric descriptionwhich is known as a layout. A layout consists of a set of planargeometric shapes in several layers.

The layout is then checked to ensure that it meets all of the designrequirements. The result is a set of design files in a particularunambiguous representation known as an intermediate form that describesthe layout. The design files are then converted into pattern generatorfiles that are used to produce patterns called masks by an optical orelectron beam pattern generator.

During fabrication, these masks are used to pattern a silicon waferusing a sequence of photolithographic steps. The component formationrequires very exacting details about geometric patterns and separationbetween them. The process of converting the specifications of anelectrical circuit into a layout is called the physical design.

Currently, the minimum geometric feature size of a component is on theorder of less than 45 nm, at the process node of 45 nm. Feature sizeswill be reduced even further as technology progresses. This smallfeature size allows fabrication of many transistors on a chip. Thistrend is expected to continue, with even smaller feature geometries andmore circuit elements on an integrated circuit, and of course, largerdie (or chip) sizes will allow far greater numbers of circuit elementson them.

ASIC design flow is a combination of logical design and physical design,and includes a variety of steps, which include and are not limited todesign entry, logic synthesis, system partitioning, floorplanning,placement, routing, and simulation, with constant feedback in theseprocesses. The objective of physical design is to determine an optimalarrangement of devices in a plane or in a three dimensional space, andan efficient interconnection or routing scheme between the devices toobtain the desired functionality. Libraries characterize differentdevices and components used in the ASIC design flow, with the componentssimulated according to the program SPICE (Simulation Program withIntegrated Circuit Emphasis), a general purpose analog electroniccircuit simulator used in IC design to check the integrity of circuitdesigns and to predict circuit behavior. Libraries exist to characterizesemiconductor devices at various parameters including process node,voltage, temperature and the like.

ASIC designers further need a timing model for each cell used in an ASICto determine the performance of the ASIC, including timing closure.Timing closure includes the ability of an ASIC cell or block to transmitand/or process a signal within specified time parameters in aspecification. Various types of delay exist in an IC including but notlimited to pin-to-pin delay between input and output pins of a logiccell, pin delay, and net or wire delay. Typically it is tootime-consuming to build every cell in silicon and measure actual celldelays, instead, designers simulate the delay in a cell, a processcalled characterization.

Due to the large number of components and the exacting details requiredby the fabrication process, logical and physical design is not practicalwithout the aid of computers. As a result, most phases of physicaldesign extensively use Computer Aided Design (CAD) tools, and manyphases have already been partially or fully automated. Automation of thephysical design process has increased the level of integration, reducedturn around time and enhanced chip performance.

In an ASIC, the layout design process involves several steps. The inputto the physical design problem is a circuit diagram, and the output isthe layout of the circuit. This is accomplished in several stagesincluding partitioning, floor planning, placement, routing andcompaction.

Regarding partitioning, a chip may contain several million transistors.Layout of the entire circuit cannot be handled due to the limitation ofmemory space as well as the computation power available. Therefore, thelayout is normally partitioned by grouping the components into blockssuch as sub-circuits and modules. The actual partitioning processconsiders many factors such as the size of the blocks, number of blocksand number of interconnections between the blocks.

The output of partitioning is a set of blocks, along with theinterconnections required between blocks. The set of interconnectionsrequired is the netlist. In large circuits, the partitioning process isoften hierarchical, although non-hierarchical (e.g. flat) processes canbe used, and at the topmost level a circuit can have between 5 to 25 ormore blocks. However, greater numbers of blocks are possible andcontemplated. Each block is then partitioned recursively into smallerblocks.

Regarding floor planning and placement, this step is concerned withselecting good layout alternatives for each block of the entire chip, aswell as between blocks and to the edges. Floor planning is a criticalstep as it sets up the ground work for a good layout. During placement,the blocks are exactly positioned on the chip. The goal of placement isto find a minimum area arrangement for the blocks that allows completionof interconnections between the blocks. Placement is typically done intwo phases. In the first phase, an initial placement is created. In thesecond phase, the initial placement is evaluated and iterativeimprovements are made until the layout has minimum area and conforms todesign specifications.

Regarding routing, the objective of the routing phase is to complete theinterconnections between blocks according to the specified netlist.First, the space not occupied by blocks, which is called the routingspace, is partitioned into rectangular regions called channels. The goalof a router is to complete all circuit connections using the shortestpossible wire length and using only the channel. Routing is usually donein two phases referred to as the global routing and detailed routingphases. In global routing, connections are completed between the properblocks of the circuit disregarding the exact geometric details of eachwire and terminal. For each wire, a global router finds a list ofchannels that are to be used as a passageway for that wire. In otherwords, global routing specifies the loose route of a wire throughdifferent regions of the routing space.

Global routing is followed by detailed routing which completespoint-to-point connections between terminals on the blocks. Looserouting is converted into exact routing by specifying the geometricinformation such as width of wires and their layer assignments. Detailedrouting includes the exact channel routing of wires.

In order for circuit designers to calculate the performance of ASICs,the designers need to compute the delays of the cells in the ASICs. Twotypes of delays are considered. The first type of delay is thepropagation delay of a cell. A propagation delay of a cell is defined asthe time duration a signal takes to travel from the input to the outputof a cell. The measurement point at the input is called the switchingthreshold. A propagation delay of a cell is defined for every input tooutput pin combination of a cell under both the rising and falling inputconditions. The propagation delay is also affected by a given process(P), voltage (V) and temperature (T).

The second type of delay is the setup/hold time delay which is an inputconstraint for sequential cells. The setup time is defined as the timeduration a data signal is required to be available at the input of acell before the clock signal transition, and the hold time is defined asthe time duration a data signal is required to be stable after the clocksignal transition. For the purpose of explanation, both propagationdelay and setup/hold time, can be referred as delay.

As the semiconductor industry advances to a smaller process node,especially 90 nm and below, there is a need for more sign-off corners inSTA (statistical timing analysis). Corners is a term of art and may bethought of as extremes in process (P), voltage (V) and temperature (T)at which a circuit design has to achieve timing closure for a particulartime requirement and operate according to specification; a sign-off is aguarantee that the circuit can perform at a particular cornercombination. A sign-off corner is thus a sort of factor of safety that achip or ASIC can operate satisfactorily.

However, more sign-off corners have a drawback: more library generationat each specific corner, which results in tremendous characterizationtime. By way of example, a cell library may have as parameters threeexternal variables P (process, i.e., N-doped/P-doped parameters at aparticular feature size), T (temperature) and V (voltage), with each ofthese variables being split into nominal (NOM), best case (BC) or worsecase (WC), to factor in a factor of safety, with temperature varyingfrom a low of say −40 C to a high of 125 C, and voltage varying +/−10%from VDD. If one were to generate all corner libraries for all thedifferent PVT combinations to satisfy all possible customers, theremight be over twenty combinations, such as: BC PVT (best case for P, Vand T); BC PV+WC T (best case for P, V and worse case for T); BC P+WC VT(best case for P, worse case for V and T); WC PVT (worse case P, V andT); WC PV+BC T (worse case P, V and best case T); and WC P+BC VT (worsecase P and best case V, T).

A derating equation is used to rapidly compute the delay in an ASICcell; otherwise calculating delay would take longer. The deratingequation(s) used by the assignee of the present invention to compute thedelay of a cell for a given P, V and T of a cell is given by U.S. Pat.No. 6,820,048 (the '048 patent), issued to Bhutani et al. (Nov. 16,2004), and U.S. Pat. No. 6,484,297 (the '297 patent), issued to Dixit etal. (Nov. 19, 2002), all incorporated herein by reference in theirentireties.

Further, the following equations are used for deratings, which arederivatives of the equations in the '048 and '297 patents:DelayCorner=Delay0+(K1*V*Fanout+K2*V*Ramptime+K3V*Fanout*Ramptime+K4V)*DeltaV  Equation1DelayCorner=Delay0+(K1*T*Fanout+K2*T*Ramptime+K3T*Fanout*Ramptime+K4T)*DeltaV  Equation2

where: Delay0 is a prior delay; K1, K2 are derating equation factors asdescribed in the '297 and '048 patents; T, V are temperature andvoltage; and Fanout, Ramptime are the fan-out and ramptime of the ASICcomponents under investigation.

The above equation is also equally good for other timing considerationslike setup/hold. When calculating delay, a cell delay library is used,with the cell delay library including a table for each timing arc in thelibrary, indexed by input ramptime and output fanout load. The basecorner library is then characterized for delay values, at four points.The delay number of these four points plus equations (1) and (2) is usedto calculate the four K factors. Once the K factors are obtained,another library can be generated from this base library, using equations(1) and (2). However, since equations (1) and (2) are linear withrespect to V and T, and vary as the square with respect to Fanout andRamptime, the delay vs. PVT is highly nonlinear, and this causes adecrease in accuracy when a corner library is far away from the basecorner.

What is lacking in the prior art is a method and apparatus for animproved process to calculate delay and to generate libraries for ASICcomponents during STA, such as taught in the present invention.

SUMMARY OF THE INVENTION

Accordingly, an aspect of the present invention is a method to increasethe accuracy when generating delay calculations when characterizing ASICcells in low submicron processes.

A further aspect of the present invention is a method of using multiplederating factors for different STA sign-off corners.

Another aspect of the present invention is a method of increasing theaccuracy of delay calculations and library generation at corners otherthan standard corners, such as off-corners.

Another aspect of the present invention is keep the library generationtime to a minimum while maintaining acceptable accuracy.

Yet another aspect of the present invention is to propose a method fordelay calculation flow to use multi-set of multi-point derating factorsK, to do delay calculations or to generate off-corner libraries in STAtiming sign off, all the while keeping the characterized base librarycalculation numbers to a minimum, speeding up the delay andcharacterization.

Thus the present invention enables a fast, accurate way for timinglibrary generation for deep sub-micron semiconductors.

The sum total of all of the above advantages, as well as the numerousother advantages disclosed and inherent from the invention describedherein, creates an improvement over prior techniques.

The above described and many other features and attendant advantages ofthe present invention will become apparent from a consideration of thefollowing detailed description when considered in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Detailed description of preferred embodiments of the invention will bemade with reference to the accompanying drawings. Disclosed herein is adetailed description of the best presently known mode of carrying outthe invention. This description is not to be taken in a limiting sense,but is made merely for the purpose of illustrating the generalprinciples of the invention. The section titles and overall organizationof the present detailed description are for the purpose of convenienceonly and are not intended to limit the present invention.

FIG. 1 is a basic flowchart for achieving the present invention.

FIG. 2 is data illustrating the improvement in performance over priortechniques in accordance with the present invention.

It should be understood that one skilled in the art may, using theteachings of the present invention, vary embodiments shown in thedrawings without departing from the spirit of the invention herein. Inthe figures, elements with like numbered reference numbers in differentfigures indicate the presence of previously defined identical elements.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is a method to insert multiple corner deratingsfor delay calculations and library generation in a multi-corner STAsign-off methodology. An apparatus and method is disclosed tocharacterize a new process using an improved delay calculation. Multiplederating factors are used for different STA sign off corners. Theapproach of the present invention does not add any extra work in celllibrary characterization, while in the mean it increases the accuracy ofthe delay calculation and the library generation at corners other thanstandard corners.

In a preferred embodiment, the method and apparatus of the presentinvention can employ a mainframe or personal computer to run anysoftware tool that incorporates the invention, and in general anycompatible piece of hardware or virtual machine can run the presentinvention, in particular during the logical and physical design of acircuit such as an ASIC. Thus a preferred method and apparatus of thepresent invention is a computing platform running a software tool, whichcan accept human input, and may be written in any computer language(such as C, C++, Perl, Java or the like), and/or an Object Orientedprogramming (OOP) language, run by a computer system having an operatingsystem. The computer system typically has one or more processors,primary and secondary memory cooperating with the processor(s), whichexecutes instructions stored in the memory, I/O means such as monitor,mouse and keyboard, and any necessary specialized hardware or firmware.Depending on the language used to construct and implement the softwaretool, the object code of the tool may have any number of classes,functions, objects, variables, templates, lines of code, portions ofcode and constructs (collectively and generally, “a process step”,“step”, “block”, “method”, “module”, “functional module” or “softwaremodule”) to carry out the invention in successive stages as describedand taught herein, and may be either a standalone software application,or employed inside of or called by another software application, or asfirmware. The software process or software module may be constructed sothat one portion of code in the application performs a plurality offunctions, as for instance in Object Oriented programming (e.g., anoverloaded process). The converse is also true, in that a plurality ofportions of code could perform a plurality of functions, and still befunctionally the same as a single portion of code. At any stage of theprocess step of the present invention, intermediate values, variablesand data may be stored for later use by the program.

Turning attention now to FIG. 1, the flowchart of the present inventionis shown. The steps of the flowchart are not necessarily rigid andstructured to flow from a first step A to a second step B, but are morefree flowing, as indicated by the boxes and the arrows, which representa number of steps within each box, consistent with the complex,multifaceted steps associated with ASIC design.

Thus, a first step would be to characterize the libraries forming thebase corners, from which the so-called off-corner libraries aremeasured. In FIG. 1, this step is illustrated by box 105 labeled“Characterized Libraries At 3 Base Corners”. Characterization may beperformed by standard ASIC tools for this purpose, known per se in theart, which may be homegrown or commercial products, e.g. such asNanoChar by Synopsys. For purposes of this invention, the base cornerlibraries or base corner points chosen from the set of all possiblelibraries or points include: BC PVT (best case for P, V and T); NOM PVT(nominal case for P, V and T); and WC PVT (worse case for P, V and T).Note this is a smaller set of base corner points than the set of allpossible corner libraries or points that can be generated for all thedifferent PVT combinations, such as indicated in the background of theinvention, hence these base corner library points or base corners can betermed a limited set of base corner library points from the set of allpossible library points.

Next, a second step would be to derive two sets (four points) to be usedfor calculating derating K factors at near and far ends of the spectrumof parameters from the base corner voltage (V) and temperature (T)parameters, given a particular process, called “off-corner” points. Thisis indicated in FIG. 1 by the step box 110 labeled “Characterized At 4Other Points At Near And Far End Of The Base Corner VT”. At these pointsSTA is performed by standard ASIC tools for this purpose, known per sein the art, e.g. such as by NanoChar. Hence, to give but one example, ifthe base corner library is BC PVT (best case for P, V and T), then twosets of off-corner points would be:

Off-corner point A: BC PV+WCT (best case P, V and worse case T)

Off-corner point B: BC PV+BCT+ΔT (best case P, V and best case T plus asmall deviation/perturbation in temperature, ΔT)

Off-corner point C: BC PT+WCV (best case P, T and worse case V)

Off-corner point D: BC PT+BCV+ΔV (best case P, T and best case V plus asmall deviation/perturbation in voltage, ΔV)

To give a concrete example, but in no way limiting, for a 90 nm processnode (the parameter(s) for a particular process node being shared incommon by the base corner library and off-corner points) a best casetemperature (BCT) might be a low temperature such as −40 C, while aworse case temperature (WCT) might be a high temperature such as 125 C,while a best case voltage (BCV) might be a high voltage like using thesupply voltage plus 10%, i.e., VDD+10%, while a worse case voltage (WCV)might be a low voltage like using the supply voltage minus 10%, i.e.,VDD−10%. The off-corner points A, C, above, involving the worse case fortemperature and voltage, are termed “far” points to the base corner,while the off-corner points B, D above, involving the best case fortemperature and voltage, and a small perturbation Δ as shown, are termedthe “near” points to the base corner. The above values for near and farpoints are only illustrative and not limiting. For example, the nearpoint temperature might be slightly higher than the nominal temperatureyet still be considered a near point. For instance, say the nominal basecase temperature is 25 C; the far point temperature might be 125 C,which is hot and deleterious long term, while the near point temperaturemight be say 35 C, slightly higher than the nominal base casetemperature. Yet the nomenclature of “near” and “far” would still hold.

The far off-corner points are used mainly for legacy purposes forenabling computation using libraries and methodologies from largerprocess nodes (i.e., using libraries and calculations from 130 nm in a90 nm process), while the near off-corner points are used mainly forpresent processes.

Off-corner points are likewise chosen for the other remaining basecorners, i.e. in the example herein for base corners NOM PVT and WC PVT.Hence these off-corner points would be as follows:

For the NOM PVT (Nominal P, V and T) base corner:

Off-corner point A2: NOM PV+WCT (nominal P, V and worse case T)

Off-corner point B2: NOM PV+BCT+ΔT (nominal P, V and best case T plus asmall deviation/perturbation temperature, ΔT)

Off-corner point C2: NOM PT+WCV (nominal P, T and worse case V)

Off-corner point D2: NOM PT+BCV+ΔV (nominal P, T and best case V plus asmall deviation/perturbation voltage, ΔV)

The off-corner “far” points above would be A2, C2, while the off-corner“near” points would be B2, D2.

For the WC PVT (Worse case P, V and T) base corner:

Off-corner point A3: WC PV+WCT+ΔT (worse case P, V and worse case T plusa small deviation/perturbation temperature, ΔT)

Off-corner point B3: WC PV+BCT (worse case P, V and best case T)

Off-corner point C3: WC PT+WCV+ΔV (worse case P, T and worse case V plusa small deviation/perturbation voltage, ΔV)

Off-corner point D3: WC PT+BCV (worse case P, T and best case V).

The off-corner “far” points above would be B3, D3, while the off-corner“near” points would be C3, A3.

The above example for off-corner points and particular base corners arerepresentative rather than limiting, and other base corners andoff-corner points may be chosen by one of ordinary skill from theteachings herein.

Next, in step 115 in FIG. 1, at the box labeled “Build Libraries At 3Base Corners, Calculate 4 K Derating Factors At Near And Far End Of TheBase Corner VT”, using the methodology of the present invention, asimplemented by suitable computer hardware, one will build librariesassociated with the circuit components at the three base corners (in ourexample BC PVT, NOM PVT and WC PVT). Libraries may be built usingstandard off-the-shelf third party programs, as is known per se,including but not limited to NanoChar, and SPICE or HSPICE by Synopysis.

Further, at step 115, the K derating factors are computed for theoff-corner points for all the near and far points, for every two sets ofoff-corner points as described herein, for each of the three basecorners. The two sets of derating K factors are calculated for each basecorner using eq. (1) and (2) as described in the background of theinvention, and the methodology of the '048 and '297 patents.

Next, in step 120 of the box in FIG. 1 labeled “Build Libraries At OffCorners Using K Factors With VT Near The Base Corner Library”, theresults from step 115 are used to build libraries, using commercialoff-the-shelf programs including but not limited to SPICE, using the Kfactors and using the near off-corner points for V, T, as explainedherein. From a SPICE correlation result it was found that that accuracyimproved by two-fold over prior techniques, as explained more fully inFIG. 2.

Finally, in step 125 of the box of FIG. 1 labeled “Do Delay CalculationAnd Deratings Using K Factors With VT Near the Base Corner Library”, theK factors are used from step 115, as explained and derived herein, tohelp compute delay calculations for the near off-corner points for V, Tfor the delay in the ASIC under consideration.

Numerous base corners may be chosen, as can be appreciated by one of ofordinary skill in the art; the examples given in a preferred embodimentherein are merely illustrative.

Turning attention now to FIG. 2, there is shown data illustrating theimprovement in performance over prior techniques in accordance with thepresent invention. As indicated herein, when comparing SPICEcalculations up to a two-fold improvement in accuracy is possible overprior techniques. Further, an experiment was performed to test theaccuracy of the present invention, and summarized in FIG. 2, where therise timing delay for a cell termed “nd2m1d” was found, the A to Z risetiming delay from data in the present assignee's LSI Glxd 13 nmtechnology. For an off-corner consisting of WC PV+BC T, the data ofcolumns labeled % Diff1 and % Diff2 in FIG. 2 show the accuracy of thedelay number with respect to a so-called “golden characterizationnumber”. The golden characterization number value is the exact valuethat would be computed by a “golden” (or exact) simulator like HSPICE,and this is the value that is being predicted by the model of thepresent invention. In FIG. 2, the column % Diff1 is using the K factorsobtained near the base corner WC PVT, while the column % Diff2 is usingthe K factors obtained from near the off-corner WC PV+BT. Generallythese percentage differences in accuracy are very satisfactory, giventhe time constraints.

In addition, the two sets of deratings factors for each off-corner arealso good for calculating not only the propagation delays and outputslew rates, but are also good for computing setup and hold times;collectively termed delay for the ASIC being constructed in accordancewith the present invention.

Although the present invention has been described in terms of thepreferred embodiments above, numerous modifications and/or additions tothe above-described preferred embodiments would be readily apparent toone skilled in the art.

It is intended that the scope of the present invention extends to allsuch modifications and/or additions and that the scope of the presentinvention is limited solely by the claims set forth below.

We claim:
 1. Computer executable program code embodied in anon-transitory computer usable medium for configuring a processor tocompute the delay of an integrated circuit (IC), said computerexecutable code comprising: a base corner module for characterizinglibraries, for an IC being constructed, about three base corner pointscomprising BC PVT, NOM PVT and WC PVT; an off-corner module forcalculating K factors for four off-corner points to the base cornerpoints; and, a delay computing module for calculating delay for theoff-corner points using the K factors; wherein: the delay of the IC iscalculated using the off-corner point K factors; and the off-cornerpoints comprise: for base corner BC PVT (best case for P, best case Vand best case T): Off-corner point A: BC PV+WCT (best case P, best caseV and worse case T) Off-corner point B: BC PV+BCT+ΔT (best case P, bestcase V and best case T plus a perturbation in temperature, ΔT)Off-corner point C: BC PT+WCV (best case P, best case T and worse caseV) Off-corner point D: BC PT+BCV+ΔV (best case P, best case T and bestcase V plus a perturbation in voltage, ΔV); and, for the NOM PVT(Nominal P, nominal V and nominal T) base corner: Off-corner point A2:NOM PV+WCT (nominal P, nominal V and worse case T) Off-corner point B2:NOM PV+BCT+ΔT (nominal P, nominal V and best case T plus a perturbationtemperature, ΔT) Off-corner point C2: NOM PT+WCV (nominal P, nominal Tand worse case V) Off-corner point D2: NOM PT+BCV+ΔV (nominal P, nominalT and best case V plus a perturbation voltage, ΔV); and, for the WC PVT(Worse case P, worse case V and worse case T) base corner: Off-cornerpoint A3: WC PV+WCT+ΔT (worse case P, V and worse case T plus aperturbation temperature, ΔT) Off-corner point B3: WC PV+BCT (worse caseP, worse case V and best case T) Off-corner point C3: WC PT+WCV+ΔV(worse case P, worse case T and worse case V plus a perturbationvoltage, ΔV) Off-corner point D3: WC PT+BCV (worse case P, worse case Tand best case V).
 2. The invention according to claim 1, wherein: thebase corner module characterizes libraries about base corner points froma limited set of base corner library points from a set of all possiblelibrary points; and an off-corner characterization module forcharacterizing libraries, for the IC being constructed, about theoff-corner points to the base corner points.
 3. The invention accordingto claim 2, wherein: each of the base corner points have at least twooff-corner points; the base corner points and off-corner points of thebase corner points have parameters from a particular process node andparameters of voltage and temperature.
 4. The invention according toclaim 3, wherein: each of the base corner points are associated with atleast four off-corner points comprising two sets of near and faroff-corner points.
 5. The invention according to claim 4, wherein: onenear point of each base corner point comprises a parameter of a bestcase temperature, and one far point of each base corner point comprisesa parameter of a worse case temperature, with the near point temperatureparameter being a temperature closer to the temperature of the basecorner point than the far point temperature parameter; and one nearpoint of each base corner point comprising a parameter of a normalsupply voltage for the IC being constructed plus an increment above thenormal supply voltage, and a far point of each base corner pointcomprising a parameter of a normal supply voltage for the IC beingconstructed plus an increment below the normal supply voltage.
 6. Theinvention according to claim 5, further comprising: a module forbuilding libraries at the plurality of off-corner points using the Kfactors, and using the near point, best case temperature and near point,best case voltage for each near off-corner point.
 7. The inventionaccording to claim 6, wherein: the delay computing module computingdelay for the IC according to the K factors for at least one of the nearpoint temperature and voltage parameters.
 8. The invention according toclaim 7, wherein: the base corner module characterizes the delay in theIC and the delay computing module computes the delay for the IC wherethe delay comprises propagation delay and output slew rates; and, theprocess node is 90 nm, the best case temperature ranges from −40 C to 35C, while the near point voltage varying from zero to +10% above thenormal supply voltage.
 9. The invention according to claim 1, furthercomprising: a module for building libraries at the plurality ofoff-corners using the K factors, and the near point temperature and bestcase voltage for each of: points B, D for the base corner BC PVT; pointsB2, D2 for the base corner NOM PVT; and points B3, D3 for the basecorner WC PVT; and, a delay computing module computing delay for the ICaccording to the K factors for the near points B, D; B2, D2 and A3, C3.10. A method for computing the delay in an integrated circuit (IC),executed by a processor, comprising the steps of: characterizing the ICabout three base corner points BC PVT, NOM PVT and WC PVT;characterizing the IC about four off-corner points associated with theeach of the base corner points; calculating K factors for the off-cornerpoints to the base corner points; calculating a delay for the ICaccording to the K factors calculated for each of the off-corner points,building libraries for the IC at each of the off-corner points; wherein:delay is calculated using the K factors for each of the off-cornerpoints; and the near and far off-corner points comprise, for each of thebase corner points: for base corner BC PVT (best case for P, best case Vand best case T): Off-corner point A: BC PV+WCT (best case P, best caseV and worse case T) Off-corner point B: BC PV+BCT+ΔT (best case P, bestcase V and best case T plus a perturbation in temperature, ΔT)Off-corner point C: BC PT+WCV (best case P, best case T and worse caseV) Off-corner point D: BC PT+BCV+ΔV (best case P, best case T and bestcase V plus a perturbation in voltage, ΔV); and, for the NOM PVT(Nominal P, nominal V and nominal T) base corner: Off-corner point A2:NOM PV+WCT (nominal P, nominal V and worse case T) Off-corner point B2:NOM PV+BCT+ΔT (nominal P, nominal V and best case T plus a perturbationtemperature, ΔT) Off-corner point C2: NOM PT+WCV (nominal P, nominal Tand worse case V) Off-corner point D2: NOM PT+BCV+ΔV (nominal P, nominalT and best case V plus a perturbation voltage, ΔV); and, for the WC PVT(Worse case P, worse case V and worse case T) base corner: Off-cornerpoint A3: WC PV+WCT+ΔT (worse case P, worse case V and worse case T plusa perturbation temperature, ΔT) Off-corner point B3: WC PV+BCT (worsecase P, worse case V and best case T) Off-corner point C3: WC PT+WCV+ΔV(worse case P, worse case T and worse case V plus a perturbationvoltage, ΔV) Off-corner point D3: WC PT+BCV (worse case P, worse case Tand best case V).
 11. The method according to claim 10, furthercomprising the steps of: forming off-corner points to each of the basecorner points, with each base corner point having at least one pair ofoff-corner points.
 12. The method according to claim 11, wherein: eachof the off-corner points to the base corner points and the base cornerpoints have parameters from a particular process node and haveparameters of temperature and voltage; each of the base corner pointshave at least two off-corner points, the off-corner points having a nearpoint temperature and a near point voltage; the near point temperatureof the off-corner points being a best case temperature parameter withrespect to the temperature comprising the base corner temperature; thenear point voltage comprising a normal supply voltage for the IC plus anincrement above the normal supply voltage.
 13. The method according toclaim 12, further comprising the steps of: building libraries for the ICat the plurality of off-corners using the K factors, the near pointtemperature and near point voltage.
 14. The method according to claim13, further comprising the steps of: computing delay for the ICaccording to the K factors for the near point temperature and near pointvoltage of the off-corners.
 15. The method according to claim 14,wherein: the pair of off-corner points associated with each base cornerpoint, comprise a near point and a far point, the far point comprising afar point temperature and a far point voltage; the near point comprisesa parameter of a best case temperature, and the far point comprises aparameter of a worse case temperature, with the near point temperaturebeing a temperature closer to the temperature of the base corner pointthan the far point temperature of the base corner point; each of thebase corner points is further associated with an additional pair ofoff-corner points comprising a near point comprising a parameter of anormal supply voltage for the IC plus an increment above the normalsupply voltage, and the far point comprising a parameter of a normalsupply voltage for the IC plus an increment below the normal supplyvoltage.
 16. The invention according to claim 10, further comprising:building libraries at the plurality of off-corners using the K factors,and the temperature and voltage for each off-corner of points B, D forthe base corner BC PVT; points B2, D2 for the base corner NOM PVT; andpoints A3, C3 for the base corner WC PVT, and, computing the delay forthe IC according to the K factors for the near points B, D; B2, D2 andA3, C3.
 17. Computer executable program code embodied in anon-transitory computer usable medium for configuring a processor tocompute timing in an IC according to multiple derating factors fordifferent sign off corners, said computer executable code comprising:means for characterizing the IC about at three base corner pointscomprising BC PVT, NOM PVT and WC PVT; means for characterizing the ICabout four off-corner points associated with each of the base cornerpoints; means for calculating K factors for the off-corner points to thebase corner point; and means for calculating a delay for the ICaccording to the K factors calculated for each of the off-corner points,means for building libraries for the IC at each of the off-cornerpoints; wherein: delay is calculated using the K factors for each of theoff-corner points; the means for characterizing the IC about three basecorner points characterizes libraries about base corner points from alimited set of base corner library points from the set of all possiblelibrary points; the base corner points and off-corner points associatedwith the base corner points have parameters from a particular processnode and parameters of voltage and temperature; each of the base cornerpoints are associated with exactly two pairs of off-corner pointscomprising near and far off-corner points; the near points of theoff-corner points having parameters of best case temperature, and thefar points of the off-corner points having parameters of a worse casetemperature, with the near point temperature of an off-corner being atemperature closer to the temperature of the base corner point relatedto the off-corner than the far point temperature; the off-corner pointsfurther comprising a near point voltage comprising the normal supplyvoltage for the IC plus an increment above the normal supply voltage,and the far point voltage comprising the normal supply voltage for theIC being constructed plus an increment below the normal supply voltage;the means for building libraries for the IC at each of the off-cornerpoints uses the K factors, and uses the near point, best casetemperature and near point, best case voltage for each off-corner whenbuilding libraries; and the delay for the IC is calculated using the Kfactors for the off-corner points.